The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 17, 2017

Filed:

May. 22, 2012
Applicants:

Haizhou Yin, Poughkeepsie, NY (US);

Huilong Zhu, Poughkeepsie, NY (US);

Zhijiong Luo, Poughkeepsie, NY (US);

Inventors:

Haizhou Yin, Poughkeepsie, NY (US);

Huilong Zhu, Poughkeepsie, NY (US);

Zhijiong Luo, Poughkeepsie, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/84 (2006.01); H01L 27/12 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); H01L 21/02 (2006.01); H01L 21/266 (2006.01); H01L 21/306 (2006.01); H01L 21/308 (2006.01); H01L 21/768 (2006.01); H01L 29/78 (2006.01); H01L 21/74 (2006.01); H01L 21/265 (2006.01); H01L 29/165 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1203 (2013.01); H01L 21/02529 (2013.01); H01L 21/02532 (2013.01); H01L 21/266 (2013.01); H01L 21/2652 (2013.01); H01L 21/3081 (2013.01); H01L 21/30604 (2013.01); H01L 21/743 (2013.01); H01L 21/76897 (2013.01); H01L 21/84 (2013.01); H01L 29/165 (2013.01); H01L 29/66636 (2013.01); H01L 29/66659 (2013.01); H01L 29/66772 (2013.01); H01L 29/78 (2013.01); H01L 29/78612 (2013.01); H01L 29/78648 (2013.01);
Abstract

The present invention provides a method for manufacturing a semiconductor structure, which comprises following steps: providing a substrate, which comprises upwards in order a base layer, a buried isolation layer, a buried ground layer, an ultra-thin insulating buried layer and a surface active layer; implementing ion implantation doping to the buried ground layer; forming a gate stack, sidewall spacers and source/drain regions on the substrate; forming a mask layer on the substrate that covers the gate stack and the source/drain regions, and etching the mask layer to expose the source region; etching the source region and the ultra-thin insulating buried layer under the source region to form an opening that exposes the buried ground layer; filling the opening through epitaxial process to form a contact plug for the buried ground layer. Accordingly, the present invention further provides a semiconductor structure. The present invention proposes formation of a buried ground layer contact plug, which then connects buried ground layer electrically to source region, thereby enhancing control capabilities of a semiconductor device over threshold voltages, suppressing short-channel effects and improving device performance; whereas no independent contact is required to build for the buried ground layer, which then saves device area and simplifies manufacturing process accordingly.


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