The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 17, 2017

Filed:

Aug. 27, 2015
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Rosa A. Orozco-Teran, Wappingers Falls, NY (US);

Ravikumar Ramachandran, Pleasantville, NY (US);

John A. Fitzsimmons, Poughkeepsie, NY (US);

Russell H Arndt, Fishkill, NY (US);

David L. Rath, Stormville, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 29/49 (2006.01); H01L 29/45 (2006.01); H01L 21/28 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H01L 29/417 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76897 (2013.01); H01L 21/28079 (2013.01); H01L 21/76805 (2013.01); H01L 21/76814 (2013.01); H01L 21/76831 (2013.01); H01L 21/76877 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 23/53238 (2013.01); H01L 23/53266 (2013.01); H01L 23/53295 (2013.01); H01L 29/41775 (2013.01); H01L 29/45 (2013.01); H01L 29/4958 (2013.01); H01L 29/78 (2013.01); H01L 21/76816 (2013.01); H01L 2924/0002 (2013.01);
Abstract

Embodiments of present invention provide a method of forming a semiconductor structure. The method includes forming a semiconductor structure having a first metal layer and a plurality of dielectric layers on top of the first metal layer; creating one or more openings through the plurality of dielectric layers to expose the first metal layer underneath the plurality of dielectric layers; causing the one or more openings to expand downward into the first metal layer and expand horizontally into areas underneath the plurality of dielectric layers; applying a layer of lining material in lining sidewalls of the one or more openings inside the plurality of dielectric layers; and filling the expanded one or more openings with a conductive material.


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