The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 10, 2017
Filed:
Jan. 30, 2015
Applicant:
Lattice Semiconductor Corporation, Hillsboro, OR (US);
Inventors:
Brad Sharpe-Geisler, San Jose, CA (US);
Senani Gunaratna, Los Gatos, CA (US);
Ting Yew, San Jose, CA (US);
Assignee:
LATTICE SEMICONDUCTOR CORPORATION, Portland, OR (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/00 (2006.01); H03K 19/177 (2006.01); H03K 19/0948 (2006.01);
U.S. Cl.
CPC ...
H03K 19/0013 (2013.01); H03K 19/0948 (2013.01); H03K 19/177 (2013.01);
Abstract
A programmable logic is provided that uses only NMOS pass transistors to pass a true output signal to an internal true node and to pass a complement output signal to an internal complement node. The internal true and complement nodes are cross-coupled through PMOS transistors so that the discharge of one of the internal true and complement nodes switches on a corresponding one of the cross-coupled PMOS transistors to charge a remaining one of the internal true and complement nodes.