The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 10, 2017

Filed:

Aug. 07, 2015
Applicant:

Panasonic Intellectual Property Management Co., Ltd., Osaka, JP;

Inventors:

Chiaki Kudou, Toyama, JP;

Haruyuki Sorada, Toyama, JP;

Tsuneichiro Sano, Toyama, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 21/3213 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7802 (2013.01); H01L 21/32134 (2013.01); H01L 21/32137 (2013.01); H01L 29/0865 (2013.01); H01L 29/1095 (2013.01); H01L 29/42356 (2013.01); H01L 29/42376 (2013.01); H01L 29/66712 (2013.01); H01L 21/02131 (2013.01); H01L 21/02266 (2013.01); H01L 21/02274 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A semiconductor device includes: semiconductor layer having an impurity region of a first conductivity type; a gate insulating layer, at least a part of the gate insulating layer positioned on the semiconductor layer; a gate electrode positioned on the gate insulating layer and having a first surface in contact with the part of the gate insulating film and a second surface opposite to the first surface; an interlayer insulating layer covering the gate electrode; and an electrode in contact with the impurity region. The gate electrode has a recess at a corner in contact with the second surface, in a cross section of the gate electrode perpendicular to a surface of the semiconductor layer. A cavity surrounded by the gate electrode and the interlayer insulating layer is positioned in a region including at least a part of the recess.


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