The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 10, 2017

Filed:

Nov. 07, 2014
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Huan-Chieh Su, Tianzhong Township, TW;

Cheng-Long Chen, Hsin-Chu, TW;

Ching-Hong Jiang, Hsin-Chu, TW;

Clement Hsingjen Wann, Carmel, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66795 (2013.01);
Abstract

An embodiment method includes forming a first fin and a second fin over a semiconductor substrate. The first fin includes a first semiconductor strip of a first type, and the second fin includes a second semiconductor strip of the first type. The method further includes replacing the second semiconductor strip with a third semiconductor strip of a second type different than the first type. Replacing the second semiconductor strip includes masking the first fin using a barrier layer while replacing the second semiconductor strip and performing a chemical mechanical polish (CMP) on the third semiconductor strip using a slurry that planarizes the third semiconductor strip at a faster rate than the barrier layer. In some embodiments, the method may further include depositing a sacrificial layer over a wafer containing the first and second fins and performing a non-selective CMP to substantially level a top surface of the wafer.


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