The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 10, 2017

Filed:

Jul. 31, 2015
Applicant:

Inotera Memories, Inc., Taoyuan, TW;

Inventors:

Shih-Fan Kuan, Taoyuan, TW;

Yi-Jen Lo, New Taipei, TW;

Assignee:

INOTERA MEMORIES, INC., Taoyuan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/04 (2014.01); H01L 25/065 (2006.01); H01L 23/00 (2006.01); H01L 23/538 (2006.01); H01L 23/31 (2006.01); H01L 23/522 (2006.01); H01L 25/00 (2006.01); H01L 21/52 (2006.01); H01L 21/56 (2006.01); H01L 21/768 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0652 (2013.01); H01L 21/52 (2013.01); H01L 21/565 (2013.01); H01L 21/76802 (2013.01); H01L 21/76879 (2013.01); H01L 21/823475 (2013.01); H01L 23/3114 (2013.01); H01L 23/5226 (2013.01); H01L 23/5384 (2013.01); H01L 23/5386 (2013.01); H01L 24/03 (2013.01); H01L 24/09 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 2224/02317 (2013.01); H01L 2224/02372 (2013.01); H01L 2224/02373 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/08165 (2013.01); H01L 2224/08235 (2013.01); H01L 2224/08238 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06548 (2013.01); H01L 2924/1434 (2013.01);
Abstract

A multi-device package includes a substrate, at least two device regions, a first redistribution layer, an external chip, a plurality of first connectors and a conductive contact. The two device regions are formed from the substrate, and the substrate has a first surface and a second surface opposite to the first surface. The first redistribution layer is disposed on the first surface and electrically connected to the two device regions, and the external chip is disposed on the first redistribution layer. The first connectors are interposed between the first redistribution layer and the external chip to interconnect the first redistribution layer and the external chip, and the conductive contact is extended from the second surface to the first surface of the substrate to electrically connect the device region.


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