The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 10, 2017

Filed:

May. 08, 2014
Applicant:

Ps4 Luxco S.a.r.l., Luxembourg, LU;

Inventor:

Yoshihiro Takaishi, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/52 (2006.01); H01L 23/528 (2006.01); H01L 27/088 (2006.01); H01L 21/8234 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/423 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 23/528 (2013.01); H01L 21/823487 (2013.01); H01L 27/088 (2013.01); H01L 27/092 (2013.01); H01L 29/0649 (2013.01); H01L 29/0657 (2013.01); H01L 29/1095 (2013.01); H01L 29/4236 (2013.01); H01L 29/7827 (2013.01); H01L 2924/0002 (2013.01);
Abstract

One semiconductor device includes one parallel transistor for connecting in parallel multiple vertical transistors disposed in an active region on a semiconductor substrate. The parallel transistor includes semiconductor pillars that project out in a direction perpendicular to a main surface of the semiconductor substrate; a lower diffusion layer that is disposed below the semiconductor pillars; upper diffusion layers that are each disposed on an upper section of the semiconductor pillars; and gate electrodes disposed, with a gate insulator film therebetween, on the entire side surfaces of the semiconductor pillars. The upper diffusion layers are connected to one upper contact plug that is disposed over the upper diffusion layers.


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