The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 10, 2017
Filed:
Jan. 14, 2015
Yun-seok Choi, Hwaseong-si, KR;
Hyeok-man Kwon, Suwon-si, KR;
Cha-jea JO, Incheon, KR;
Tae-je Cho, Hwaseong-si, KR;
Yun-seok Choi, Hwaseong-si, KR;
Hyeok-man Kwon, Suwon-si, KR;
Cha-jea Jo, Incheon, KR;
Tae-je Cho, Hwaseong-si, KR;
Abstract
Provided is a stacked semiconductor package which minimizes a limitation on a design of a lower semiconductor chip due to a characteristic of an upper semiconductor chip stacked on the lower chip. The stacked semiconductor package includes a lower chip having a through electrode area in which a plurality of through electrodes are disposed; and at least one upper chip stacked on the lower chip and having a pad area in which a plurality of pads corresponding to the plurality of through electrodes are disposed. The pad area is disposed along a central axis bisecting an active surface of the upper chip. The central axis where the pad area of the upper chip is disposed is placed at a position which is shifted from a central axis in a longitudinal direction of an active surface of the lower chip.