The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 10, 2017
Filed:
Nov. 28, 2011
Jian Liu, Los Gatos, CA (US);
Xiao Lin, San Jose, CA (US);
Anyu Kuo, San Jose, CA (US);
Jiayuan Fang, Saratoga, CA (US);
Jian Liu, Los Gatos, CA (US);
Xiao Lin, San Jose, CA (US);
Anyu Kuo, San Jose, CA (US);
Jiayuan Fang, Saratoga, CA (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
Methods, systems, and computer readable media are disclosed for simulating a circuit. The method may comprise a step of providing a network model of the circuit having a plurality of ports, the plurality of ports being associated with one or more net pairs. The method may also comprise combining the plurality of ports into one or more groups based on the net pairs, each group corresponding to a net pair. In addition, the method may comprise calculating, for each group, one or more expansion elements, wherein the one or more expansion elements are associated with a shared property among all ports of the group. Moreover, the method may comprise simulating the circuit using a combination of the expansion elements calculated for each group.