The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 10, 2017

Filed:

Dec. 18, 2013
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Marc Torrant, Sacramento, CA (US);

David Puffer, Tempe, AZ (US);

Blaise Fanning, Folsom, CA (US);

Bryan White, Chandler, AZ (US);

Joydeep Ray, Folsom, CA (US);

Neil Schaper, Folsom, CA (US);

Todd Witter, Orangevale, CA (US);

Altug Koker, El Dorado Hills, CA (US);

Aditya Sreenivas, Folsom, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/02 (2006.01); G06F 12/08 (2016.01); G06F 12/10 (2016.01); G06F 12/12 (2016.01);
U.S. Cl.
CPC ...
G06F 12/126 (2013.01); G06F 2212/69 (2013.01);
Abstract

A processing device comprises an instruction execution unit, a memory agent and pinning logic to pin memory pages in a multi-level memory system upon request by the memory agent. The pinning logic includes an agent interface module to receive, from the memory agent, a pin request indicating a first memory page in the multi-level memory system, the multi-level memory system comprising a near memory and a far memory. The pinning logic further includes a memory interface module to retrieve the first memory page from the far memory and write the first memory page to the near memory. In addition, the pinning logic also includes a descriptor table management module to mark the first memory page as pinned in the near memory, wherein marking the first memory page as pinned comprises setting a pinning bit corresponding to the first memory page in a cache descriptor table and to prevent the first memory page from being evicted from the near memory when the first memory page is marked as pinned.


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