The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 10, 2017
Filed:
Mar. 30, 2012
Paul Caprioli, Hillsboro, OR (US);
Matthew C. Merten, Hillsboro, OR (US);
Muawya M. Al-otoom, Beaverton, OR (US);
Omar M. Shaikh, Portland, OR (US);
Abhay S. Kanhere, Fremont, CA (US);
Suresh Srinivas, Portland, OR (US);
Koichi Yamada, Los Gatos, CA (US);
Vivek Thakkar, Sunnyvale, CA (US);
Pawel Osciak, Santa Clara, CA (US);
Paul Caprioli, Hillsboro, OR (US);
Matthew C. Merten, Hillsboro, OR (US);
Muawya M. Al-Otoom, Beaverton, OR (US);
Omar M. Shaikh, Portland, OR (US);
Abhay S. Kanhere, Fremont, CA (US);
Suresh Srinivas, Portland, OR (US);
Koichi Yamada, Los Gatos, CA (US);
Vivek Thakkar, Sunnyvale, CA (US);
Pawel Osciak, Santa Clara, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A hardware profiling mechanism implemented by performance monitoring hardware enables page level automatic binary translation. The hardware during runtime identifies a code page in memory containing potentially optimizable instructions. The hardware requests allocation of a new page in memory associated with the code page, where the new page contains a collection of counters and each of the counters corresponds to one of the instructions in the code page. When the hardware detects a branch instruction having a branch target within the code page, it increments one of the counters that has the same position in the new page as the branch target in the code page. The execution of the code page is repeated and the counters are incremented when branch targets fall within the code page. The hardware then provides the counter values in the new page to a binary translator for binary translation.