The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 10, 2017
Filed:
Jun. 25, 2013
Applicants:
Simon Rubanovich, Haifa, IL;
Thierry Pons, Hadera, IL;
Amit Gradstein, Binyamina, IL;
Zeev Sperber, Zichron Yaakov, IL;
Inventors:
Simon Rubanovich, Haifa, IL;
Thierry Pons, Hadera, IL;
Amit Gradstein, Binyamina, IL;
Zeev Sperber, Zichron Yaakov, IL;
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/483 (2006.01); G06F 7/544 (2006.01); G06F 7/76 (2006.01);
U.S. Cl.
CPC ...
G06F 7/483 (2013.01); G06F 7/5443 (2013.01); G06F 7/764 (2013.01);
Abstract
Systems and methods of performing a fused multiply add (FMA) operations are provided. In one embodiment, the length of the adder used by the FMA operation is less than 3*N, where N is the number of bits in the mantissa term of a floating point number. A mask may be used to perform the addition portion of the FMA operation using the adder. A second mask may be used to denormalize the result of the addition portion of the FMA operation if an underflow occurs.