The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 10, 2017

Filed:

Oct. 22, 2015
Applicant:

Intel Corporation, Snta Clara, CA (US);

Inventors:

Barnes Cooper, Tigard, OR (US);

Jeffrey R Wilcox, El Dorado Hills, CA (US);

Michael N Derr, El Dorado Hills, CA (US);

Neil W Songer, Santa Clara, CA (US);

Craig S Forbell, Los Gatos, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/32 (2006.01);
U.S. Cl.
CPC ...
G06F 1/3206 (2013.01); G06F 1/3234 (2013.01); G06F 1/3243 (2013.01); Y02B 60/1239 (2013.01);
Abstract

In an embodiment, a processor includes a plurality of cores and power management logic. The power management logic may be to, in response to a first break event during a reduced power state in the processor, set an exit timer based on a platform latency tolerance, block a first plurality of break events from interrupting the reduced power state, and in response to a expiration of the exit timer, terminate the reduced power state. Other embodiments are described and claimed.


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