The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 10, 2017

Filed:

May. 08, 2013
Applicants:

Harmander Singh, Austin, TX (US);

Mohammad Mehedi Hasan, Austin, TX (US);

Abhiman Pratap Kotwal, Austin, TX (US);

Gianfranco Gerosa, Austin, TX (US);

Mohammed Hasan Taufique, Austin, TX (US);

Inventors:

Harmander Singh, Austin, TX (US);

Mohammad Mehedi Hasan, Austin, TX (US);

Abhiman Pratap Kotwal, Austin, TX (US);

Gianfranco Gerosa, Austin, TX (US);

Mohammed Hasan Taufique, Austin, TX (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02H 3/20 (2006.01); H02H 9/04 (2006.01); G01R 19/165 (2006.01); G11C 7/04 (2006.01); G11C 7/24 (2006.01); G11C 5/14 (2006.01); H01L 27/02 (2006.01); H02H 9/00 (2006.01); H02H 3/22 (2006.01); G11C 16/22 (2006.01);
U.S. Cl.
CPC ...
G01R 19/165 (2013.01); G11C 5/143 (2013.01); G11C 7/04 (2013.01); G11C 7/24 (2013.01); H01L 27/0248 (2013.01); G11C 16/22 (2013.01);
Abstract

Described is an apparatus comprising: a voltage level detector to monitor a first power supply node; and a voltage level protector, coupled to the voltage level detector, to protect the voltage level detector from receiving a power supply on the first power supply node above a pre-defined threshold voltage. Described is also a voltage level protector to protect a first power supply node from receiving a power supply above a pre-defined threshold voltage, the voltage level protector comprising: a first p-type device coupled to a second power supply node, the second power supply node to receive a power supply higher than the power supply on the first power supply node; and a second p-type device coupled in series to the first p-type device, the second p-type further coupled to the first power supply node, which is for coupling to a voltage level detector.


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