The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 10, 2017

Filed:

Oct. 30, 2015
Applicant:

Freescale Semiconductor, Inc., Austin, TX (US);

Inventors:

Md M. Hoque, Gilbert, AZ (US);

Weize Chen, Phoenix, AZ (US);

Patrice M. Parris, Phoenix, AZ (US);

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01N 27/414 (2006.01); G01N 27/333 (2006.01);
U.S. Cl.
CPC ...
G01N 27/333 (2013.01); G01N 27/414 (2013.01);
Abstract

A mechanism is provided for enhancing the sensitivity of an ion-sensitive semiconductor device by creating a second gate coupled to a sense plate that can improve the amount of charge brought to the ion-sensitive semiconductor device conductivity modulated region (e.g., a channel region of an ISFET). This is accomplished by utilizing a buried dielectric layer associated with the ion-sensitive semiconductor device conductivity modulated region as the second gate dielectric. The buried dielectric layer is coupled to the sense plate using an isolated well region as a conductor that is coupled to metal layers extending to the sense plate. Some embodiments further use the buried dielectric layer as the sole gate dielectric for the semiconductor device, thereby allowing the traditional gate dielectric region to be coupled to a protection diode. This protection diode then protects the gate dielectric from plasma induced damage and electrostatic discharge.


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