The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 03, 2017
Filed:
Feb. 09, 2015
Applicant:
Qualcomm Incorporated, San Diego, CA (US);
Inventor:
Pratyush Kamal, San Diego, CA (US);
Assignee:
QUALCOMM Incorporated, San Diego, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/356 (2006.01); H03K 3/012 (2006.01); H03K 3/3562 (2006.01); G11C 19/28 (2006.01); H01L 27/06 (2006.01); G11C 19/34 (2006.01);
U.S. Cl.
CPC ...
H03K 3/356182 (2013.01); G11C 19/28 (2013.01); G11C 19/34 (2013.01); H01L 27/0688 (2013.01); H03K 3/012 (2013.01); H03K 3/35606 (2013.01); H03K 3/35625 (2013.01);
Abstract
A 3D multi-bit flip-flop may include a two tier structure. The two tier structure may include a first tier containing a common clock circuit for the multi-bit flip-flop as well as the clock driven portions of the individual flip-flops and a second tier containing a common scan circuit for the multi-bit flip-flop as well as the non-clock driven portions of the individual flip-flops. Alternatively, the first tier may include the common clock circuit as well as a portion of the individual flip-flops and the second tier may include the common scan circuit as well as the other portion of the individual flip-flops.