The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 03, 2017

Filed:

Nov. 24, 2014
Applicant:

Shanghai Ic R & D Center Co., Ltd., Shanghai, CN;

Inventors:

Chunyan Yi, Shanghai, CN;

Ming Li, Shanghai, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/027 (2006.01); H01L 21/308 (2006.01); H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66795 (2013.01); H01L 21/0276 (2013.01); H01L 21/3086 (2013.01); H01L 21/31116 (2013.01); H01L 21/31138 (2013.01);
Abstract

A line-end cutting method for fin structures of FinFETs formed by double patterning technology firstly utilizes the SiN hard mask lines to form fin structures and then performs lithography and etching processes to form line-end cuts. Since the depth of the line-end cuts is large, there is enough time and space to regulate the etching recipe so as to balance the etching rate of multiple layers including the spin-on-carbon layer, the SiN layer, the SiOlayer and the silicon substrate, thereby forming the fin structures with line-end cuts having flatter bottom topography, preventing the formation of silicon protrusions or silicon cones during the etching process and improving the device electrical performance.


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Yi, Chunyan. (2017). Line-end cutting method for fin structures of finfets formed by double patterning technology (U.S. Patent No. 9536987). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9536987

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