The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 03, 2017
Filed:
May. 15, 2013
Nec Corporation, Minato-ku, Tokyo, JP;
Tohoku University, Sendai-shi, Miyagi, JP;
Ryusuke Nebashi, Tokyo, JP;
Noboru Sakimura, Tokyo, JP;
Yukihide Tsuji, Tokyo, JP;
Ayuka Tada, Tokyo, JP;
Tadahiko Sugibayashi, Tokyo, JP;
Takahiro Hanyu, Miyagi, JP;
Tetsuo Endoh, Miyagi, JP;
Hideo Ohno, Miyagi, JP;
NEC CORPORATION, Tokyo, JP;
TOHOKU UNIVERSITY, Miyagi, JP;
Abstract
A nonvolatile logic gate device is configured to include a resistive network of a memory structure in which at least three nonvolatile resistive elements are connected, a reference resistive network as a reference resistance providing a tolerance of the memory structure to a resistance value of the resistive network of the memory structure, a writing part operable to selectively write or rewrite a value of each of the nonvolatile resistive elements in the resistive network into a maximum or a minimum corresponding to a logical value to be read when data are stored into the resistive network, and a logic circuit structure operable to use, as a logical value of the memory structure, a value obtained by comparison between the resistance value of the resistive network and the resistance value of the reference resistive network.