The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 03, 2017

Filed:

Jun. 29, 2013
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Ravi Rajwar, Portland, OR (US);

Matthew C. Merten, Hillsboro, OR (US);

Christine E. Wang, Portland, OR (US);

Vijaykumar B. Kadgi, Portland, OR (US);

Rajesh S. Parthasarathy, Hillsboro, OR (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/46 (2006.01); G06F 9/38 (2006.01); G06F 9/52 (2006.01);
U.S. Cl.
CPC ...
G06F 9/467 (2013.01); G06F 9/384 (2013.01); G06F 9/3836 (2013.01); G06F 9/3842 (2013.01); G06F 9/3857 (2013.01); G06F 9/3861 (2013.01); G06F 9/3863 (2013.01); G06F 9/466 (2013.01); G06F 9/528 (2013.01);
Abstract

A processor, system, and method are described for continued retirement of operations during a commit of a speculative region of program code. For example, one embodiment of a method comprises the operations of identifying a plurality of transactional memory regions in program code, including a first transactional memory region; and retiring one or more of a plurality of operations which follow the first transactional memory region even when a commit operation associated with the first transactional memory region is waiting to complete.


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