The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 27, 2016
Filed:
Mar. 28, 2013
Applicant:
Ttm Technologies, Inc., Santa Ana, CA (US);
Inventors:
John Vesce, Somers, CT (US);
Joseph William Heery, Jr., Tolland, CT (US);
Assignee:
Other;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 3/20 (2006.01); H05K 3/36 (2006.01); H05K 3/46 (2006.01); H05K 1/02 (2006.01); H05K 3/42 (2006.01);
U.S. Cl.
CPC ...
H05K 3/36 (2013.01); H05K 3/4623 (2013.01); H05K 3/4638 (2013.01); H05K 1/0269 (2013.01); H05K 3/368 (2013.01); H05K 3/429 (2013.01); H05K 3/4691 (2013.01); H05K 2201/09063 (2013.01); H05K 2203/061 (2013.01); H05K 2203/063 (2013.01); H05K 2203/167 (2013.01); Y10T 29/49126 (2015.01);
Abstract
The invention provides a method of fabricating an interconnect comprising aligning and stacking a plurality of printed circuit boards with at least one adhesive component, laminating the printed circuit boards and the adhesive component, preparing bonded pair holes, depositing a copper seed layer, forming a copper plate image, electroplating a copper layer, removing a plate resist and depositing an insulator layer.