The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 27, 2016

Filed:

Jul. 04, 2013
Applicants:

Thierry Sicard, Auzeville Tolosane, FR;

Philippe Perruchoud, Tournefeuille, FR;

Inventors:

Thierry Sicard, Auzeville Tolosane, FR;

Philippe Perruchoud, Tournefeuille, FR;

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 3/00 (2006.01); H03K 17/567 (2006.01); H03K 17/06 (2006.01); H02M 7/5387 (2007.01);
U.S. Cl.
CPC ...
H03K 17/567 (2013.01); H03K 17/06 (2013.01); H02M 7/5387 (2013.01);
Abstract

A gate drive circuit includes a first switch and a first capacitor. A first terminal of the first capacitor is electrically coupled to the first switch. The first switch is electrically coupled between the first terminal and a voltage supply of the power transistor. A second terminal of the first capacitor is electrically coupled to the reference potential. The gate drive circuit further includes a first voltage limiter in parallel with the first capacitor. The first voltage limiter limits a voltage across the first capacitor to a first predetermined voltage. The gate drive circuit further includes a second capacitor, a pre-charging circuit arranged between the first terminal of the first capacitor and a first terminal of the second capacitor. The gate drive circuit further includes a third capacitor with a first terminal electrically coupled to a second terminal of the second capacitor and a second terminal electrically coupled to a gate terminal of the power transistor.


Find Patent Forward Citations

Loading…