The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 27, 2016

Filed:

Jul. 29, 2015
Applicant:

Infineon Technologies Americas Corp., El Segundo, CA (US);

Inventor:

Michael A. Briere, Scottsdale, AZ (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/778 (2006.01); H01L 29/66 (2006.01); H01L 29/205 (2006.01); H01L 21/02 (2006.01); H01L 21/768 (2006.01); H01L 29/20 (2006.01); H01L 29/423 (2006.01); H01L 29/80 (2006.01); H01L 29/51 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7783 (2013.01); H01L 21/02063 (2013.01); H01L 21/76814 (2013.01); H01L 29/2003 (2013.01); H01L 29/205 (2013.01); H01L 29/4232 (2013.01); H01L 29/66431 (2013.01); H01L 29/66462 (2013.01); H01L 29/778 (2013.01); H01L 29/7787 (2013.01); H01L 29/803 (2014.09); H01L 29/51 (2013.01); H01L 29/518 (2013.01);
Abstract

According to one embodiment, a III-nitride transistor includes a conduction channel formed between first and second III-nitride bodies, the conduction channel including a two-dimensional electron gas. The transistor also includes at least one gate dielectric layer having a charge confined within to cause an interrupted region of the conduction channel and a gate electrode operable to restore the interrupted region of the conduction channel. The transistor can be an enhancement mode transistor. In one embodiment, the gate dielectric layer is a silicon nitride layer. In another embodiment, the at least one gate dielectric layer is a silicon oxide layer. The charge can be ion implanted into the at least one gate dielectric layer. The at least one gate dielectric layer can also be grown with the charge.


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