The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 27, 2016

Filed:

Dec. 18, 2014
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Kangguo Cheng, Schenectady, NY (US);

Joseph Ervin, Wappingers Falls, NY (US);

Juntao Li, Cohoes, NY (US);

Chengwen Pei, Danbury, CT (US);

Geng Wang, Stormville, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/84 (2006.01); H01L 21/311 (2006.01); H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 21/3213 (2006.01); H01L 21/8234 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 21/845 (2013.01); H01L 21/02532 (2013.01); H01L 21/02546 (2013.01); H01L 21/02592 (2013.01); H01L 21/02667 (2013.01); H01L 21/31111 (2013.01); H01L 21/32133 (2013.01); H01L 21/823431 (2013.01); H01L 21/823468 (2013.01); H01L 21/823821 (2013.01); H01L 21/823864 (2013.01); H01L 29/6653 (2013.01); H01L 29/6656 (2013.01);
Abstract

An approach to forming fins for a semiconductor device on a silicon-on-insulator wafer. The approach includes depositing a layer of mandrel material and etching the layer of mandrel material to form a mandrel. The approach includes depositing a layer of a dielectric material on the semiconductor layer and around the mandrel and etching the layer of the dielectric material to form one or more spacers next to the sidewalls of the mandrel, followed by removing the mandrel. Additionally, the approach includes depositing a layer of amorphous semiconductor material around said one or more spacers and heating it to transform into a layer of re-crystallized semiconductor material through solid phase epitaxy. Furthermore, the approach includes removing portions of the layer of re-crystallized semiconductor material from each of the horizontal surfaces of the silicon-on-insulator wafer including the area where the one or more spacers were removed to form one or more fins.


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