The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 27, 2016

Filed:

Jun. 24, 2014
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Effendi Leobandung, Stormville, NY (US);

Richard S. Wise, Ridgefield, CT (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/311 (2006.01); H01L 29/66 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 27/088 (2006.01); H01L 27/12 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 21/31116 (2013.01); H01L 21/823821 (2013.01); H01L 21/823864 (2013.01); H01L 27/0924 (2013.01); H01L 29/66795 (2013.01); H01L 21/823431 (2013.01); H01L 21/823468 (2013.01); H01L 27/0886 (2013.01); H01L 27/1211 (2013.01);
Abstract

Forming a field effect transistor device includes forming first and second semiconductor fins on a semiconductor substrate. The first and second semiconductor fins are separated by a trench region. The trench region has a first sidewall corresponding to a sidewall of the first semiconductor fin and a second sidewall corresponding to a sidewall of the second semiconductor fin. A gate stack is arranged over respective channel regions of the first and semiconductor fins. A first sidewall of the gate stack corresponds to a third sidewall of the trench region. A protective layer is formed only on a bottom portion of the trench region and along the first sidewall of the gate stack. The protective layer along the first sidewall of the gate stack defines a gate spacer.


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