The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 27, 2016

Filed:

Mar. 15, 2013
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Sanjeev Kumar, San Jose, CA (US);

Christopher J. Hughes, Santa Clara, CA (US);

Partha Kundu, Palo Alto, CA (US);

Anthony Nguyen, Castro Valley, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2006.01); G06F 9/46 (2006.01); G06F 9/52 (2006.01); G06F 9/30 (2006.01); G06F 9/38 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0806 (2013.01); G06F 9/3004 (2013.01); G06F 9/30087 (2013.01); G06F 9/3857 (2013.01); G06F 9/467 (2013.01); G06F 9/528 (2013.01); G06F 12/0831 (2013.01); G06F 12/0848 (2013.01);
Abstract

Embodiments of the invention relate a hybrid hardware and software implementation of transactional memory accesses in a computer system. A processor including a transactional cache and a regular cache is utilized in a computer system that includes a policy manager to select one of a first mode (a hardware mode) or a second mode (a software mode) to implement transactional memory accesses. In the hardware mode the transactional cache is utilized to perform read and write memory operations and in the software mode the regular cache is utilized to perform read and write memory operations.


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