The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 27, 2016

Filed:

Sep. 30, 2011
Applicants:

Leena K. Puthiyedath, Portland, OR (US);

Blaise Fanning, Folsom, CA (US);

Toby Opferman, Beaverton, OR (US);

James B. Crossland, Banks, OR (US);

Inventors:

Leena K. Puthiyedath, Portland, OR (US);

Blaise Fanning, Folsom, CA (US);

Toby Opferman, Beaverton, OR (US);

James B. Crossland, Banks, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 12/02 (2006.01); G06F 12/08 (2016.01); G06F 12/06 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0238 (2013.01); G06F 12/08 (2013.01); G06F 12/0638 (2013.01); G06F 12/0866 (2013.01); G06F 2212/2024 (2013.01); G06F 2212/214 (2013.01); G06F 2212/251 (2013.01); G06F 2212/7201 (2013.01);
Abstract

A non-volatile random access memory (NVRAM) is used in a computer system to perform multiple roles in a platform storage hierarchy, specifically, to replace traditional mass storage that is accessible by an I/O. The computer system includes a processor to execute software and a memory coupled to the processor. At least a portion of the memory comprises a non-volatile random access memory (NVRAM) that is byte-rewritable and byte-erasable by the processor. The system further comprises a memory controller coupled to the NVRAM to perform a memory access operation to access the NVRAM in response to a request from the software for access to a mass storage.


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