The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 27, 2016

Filed:

May. 10, 2012
Applicants:

Shinichi Nakamura, Tokyo, JP;

Fumiaki Nanami, Tokyo, JP;

Inventors:

Shinichi Nakamura, Tokyo, JP;

Fumiaki Nanami, Tokyo, JP;

Assignee:

UNITECHNO, INC., Tokyo, JP;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/20 (2006.01); G01R 31/28 (2006.01); G01R 1/04 (2006.01); G01R 1/067 (2006.01); G01R 31/26 (2014.01);
U.S. Cl.
CPC ...
G01R 31/2893 (2013.01); G01R 1/0466 (2013.01); G01R 1/06705 (2013.01); G01R 31/2601 (2013.01);
Abstract

The semiconductor transporting and testing fixture according to the present invention comprises: a frame portion () adapted to receive therein an IC () having an external connection terminal, the frame portion having an inner peripheral wall; a bottom surface sheet () pasted on a bottom surface of the frame portion, the bottom surface sheet having an IC side pad () formed on a front surface thereof and a socket side pad () formed on a rear surface thereof, the IC side pad being adapted to contact the external connection terminal, the socket side pad electrically connected with the corresponding IC side pad and being adapted to contact a testing socket, wherein the frame portion () is provided with a retaining latch () protruding therefrom toward above the IC () when the IC () is received in the inner peripheral wall () of the frame portion ().


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