The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 20, 2016

Filed:

Feb. 05, 2015
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Srinivasa R. Banna, San Jose, CA (US);

Michael A. van Buskirk, Saratoga, CA (US);

Timothy Thurgate, Sunnyvale, CA (US);

Assignee:

Other;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01); H01L 27/108 (2006.01); H01L 27/105 (2006.01); H01L 27/12 (2006.01); H01L 29/78 (2006.01); G11C 7/00 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10802 (2013.01); G11C 7/00 (2013.01); H01L 27/105 (2013.01); H01L 27/1052 (2013.01); H01L 27/1203 (2013.01); H01L 29/0847 (2013.01); H01L 29/1029 (2013.01); H01L 29/1095 (2013.01); H01L 29/7841 (2013.01);
Abstract

Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell including a first region, a second region, and a body region capacitively coupled to at least one word line and disposed between the first region and the second region. Each memory cell also including a third region, wherein the third region may be doped differently than the first region, the second region, and the body region.


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