The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 20, 2016

Filed:

Jan. 08, 2015
Applicant:

Shinko Electric Industries Co., Ltd., Nagano-ken, JP;

Inventor:

Satoshi Shiraki, Nagano, JP;

Assignee:

Shinko Electric Industries Co., Ltd., Nagano-shi, Nagano-ken, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/12 (2006.01); H01L 23/053 (2006.01); H01L 21/20 (2006.01); H01L 21/36 (2006.01); H01L 23/498 (2006.01); H05K 1/11 (2006.01); H01L 25/10 (2006.01); H01L 23/00 (2006.01); H01L 23/538 (2006.01); H01L 23/31 (2006.01); H05K 1/14 (2006.01); H05K 3/00 (2006.01); H01L 23/29 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49838 (2013.01); H01L 23/49811 (2013.01); H01L 23/49816 (2013.01); H01L 23/49822 (2013.01); H01L 23/49833 (2013.01); H01L 24/97 (2013.01); H01L 25/105 (2013.01); H05K 1/111 (2013.01); H01L 23/295 (2013.01); H01L 23/3128 (2013.01); H01L 23/5389 (2013.01); H01L 2224/13111 (2013.01); H01L 2224/13116 (2013.01); H01L 2224/16237 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/81191 (2013.01); H01L 2224/81801 (2013.01); H01L 2224/92125 (2013.01); H01L 2224/97 (2013.01); H01L 2225/1023 (2013.01); H01L 2225/1058 (2013.01); H01L 2924/12044 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1432 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/1436 (2013.01); H01L 2924/1437 (2013.01); H01L 2924/1438 (2013.01); H01L 2924/1533 (2013.01); H01L 2924/181 (2013.01); H05K 1/144 (2013.01); H05K 3/0052 (2013.01); H05K 3/0097 (2013.01); H05K 2201/0939 (2013.01); H05K 2201/09409 (2013.01); H05K 2201/09418 (2013.01); H05K 2201/10977 (2013.01);
Abstract

A wiring substrate includes a block with substrates laid out in an array. The block includes corners and a plan view center. Each substrate includes a substrate body. Pads are formed on the substrate body. Each pad includes a pad surface. The pads of the substrates include first pads, which are the pads of one of the substrates located in at least one of the corners of the block. The pad surface of each of the first pads includes a first axis extending from the first pad toward the plan view center of the block. The pad surface of each of the first pads has a first length along the corresponding first axis and a second length along a second axis, which is orthogonal to the first axis. The first length is longer than the second length.


Find Patent Forward Citations

Shiraki, Satoshi. (2016). Wiring substrate, semiconductor package, and method for manufacturing semiconductor package (U.S. Patent No. 9524931). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9524931

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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