The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 20, 2016
Filed:
Mar. 24, 2016
Applicant:
Canon Kabushiki Kaisha, Tokyo, JP;
Inventors:
Takaaki Yamaguchi, Yokohama, JP;
Toshio Negishi, Yokohama, JP;
Taku Yokozawa, Yokohama, JP;
Hiroaki Shirakawa, Kawasaki, JP;
Kazunari Fujii, Tokyo, JP;
Assignee:
Canon Kabushiki Kaisha, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B41J 29/38 (2006.01); B41J 2/045 (2006.01);
U.S. Cl.
CPC ...
B41J 2/04541 (2013.01); B41J 2/0455 (2013.01); B41J 2/0458 (2013.01); B41J 2/04521 (2013.01); B41J 2/04523 (2013.01); B41J 2/04531 (2013.01); B41J 2/04548 (2013.01);
Abstract
A substrate includes an AND circuit and an LVC. The AND circuit generates a control signal for switching an NMOS transistor. The LVC controls the gate voltage of the NMOS transistor on the basis of the control signal. The substrate applies a constant gate voltage to a PMOS transistor without using the AND circuit and the LVC.