The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 13, 2016

Filed:

Dec. 23, 2015
Applicant:

Imec Vzw, Leuven, BE;

Inventors:

Zheng Tao, Leuven, BE;

Kaidong Xu, Leuven, BE;

Assignee:

IMEC VZW, Leuven, BE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/306 (2006.01); H01L 21/225 (2006.01); H01L 21/8238 (2006.01); H01L 21/311 (2006.01); H01L 21/308 (2006.01); H01L 21/266 (2006.01); H01L 21/84 (2006.01);
U.S. Cl.
CPC ...
H01L 21/2253 (2013.01); H01L 21/225 (2013.01); H01L 21/266 (2013.01); H01L 21/306 (2013.01); H01L 21/308 (2013.01); H01L 21/3085 (2013.01); H01L 21/30604 (2013.01); H01L 21/31144 (2013.01); H01L 21/8238 (2013.01); H01L 21/823821 (2013.01); H01L 21/845 (2013.01);
Abstract

According to an aspect of the present inventive concept there is provided a method of providing an implanted region in a semiconductor structure including a first region and a second region, the method comprising: providing a first implantation mask covering the first region of the semiconductor structure, the first implantation mask including a first sacrificial layer, wherein the first sacrificial layer is formed as a spin-on-carbon (SOC) layer, and a second sacrificial layer, wherein the second sacrificial layer is formed as a spin-on-glass (SOG) layer; subjecting the semiconductor structure to an ion implantation process wherein an extension of the first implantation mask is such that ion implantation in the first region is counteracted and ion implantation in the second region is allowed wherein the second region is implanted; forming a third sacrificial layer covering the second region of the semiconductor structure, wherein the third sacrificial layer includes carbon; removing the second sacrificial layer at the first region by etching, wherein the third sacrificial layer protects the second region from being affected by said etching; and removing the first sacrificial layer at the first region and the third sacrificial layer at the second region by etching.


Find Patent Forward Citations

Tao, Zheng. (2016). Method of providing an implanted region in a semiconductor structure (U.S. Patent No. 9520291). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9520291

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