The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 13, 2016

Filed:

Apr. 03, 2014
Applicant:

Sandisk Enterprise Ip Llc, Milpitas, CA (US);

Inventors:

David Dean, Litchfield Park, AZ (US);

Robert W. Ellis, Phoenix, AZ (US);

Assignee:

SANDISK TECHNOLOGIES LLC, Plano, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/20 (2006.01); G06F 1/20 (2006.01); G01R 31/28 (2006.01); G01R 1/04 (2006.01); G01R 31/26 (2014.01); H01L 23/467 (2006.01); H05K 1/14 (2006.01); H05K 7/20 (2006.01); G01R 31/00 (2006.01); H01L 23/498 (2006.01); H05K 1/02 (2006.01);
U.S. Cl.
CPC ...
G06F 1/20 (2013.01); G01R 1/0408 (2013.01); G01R 31/2601 (2013.01); G01R 31/2891 (2013.01); H01L 23/467 (2013.01); H01L 23/4985 (2013.01); H05K 1/147 (2013.01); H05K 7/20727 (2013.01); G01R 31/2834 (2013.01); G01R 31/2887 (2013.01); H01L 23/49833 (2013.01); H01L 2924/0002 (2013.01); H05K 1/0201 (2013.01); H05K 2201/042 (2013.01);
Abstract

Various embodiments described herein include systems, methods and/or devices for dissipating heat generated by electronic components in an electronic system (e.g., a memory system that includes closely spaced memory modules). In one aspect, an electronic assembly includes a first circuit board, a second circuit board flexibly coupled to the first circuit board, a connecting module coupled to the second circuit board, and a fastener. The fastener is configured to couple the first circuit board to the connecting module such that the first circuit board and the second circuit board are substantially parallel and are separated by a space, wherein the space forms at least part of a channel that is configured to direct airflow through the space between the first circuit board, second circuit board, and connecting module.


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