The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 06, 2016
Filed:
Oct. 15, 2015
Lam Research Corporation, Fremont, CA (US);
Paul Raymond Besser, Sunnyvale, CA (US);
Bart van Schravendijk, Sunnyvale, CA (US);
Yoshie Kimura, Castro Valley, CA (US);
Gerardo A. Delgadino, Milpitas, CA (US);
Harald Orkorn-Schmidt, Klagengurt, AT;
Dengliang Yang, Union City, CA (US);
LAM RESEARCH CORPORATION, Fremont, CA (US);
Abstract
A method for providing a FinFET device with an air gap spacer includes providing a substrate a plurality of fins and a dummy gate arranged transverse to the plurality of fins; depositing a sacrificial spacer around the dummy gate; depositing a first interlayer dielectric (ILD) layer around the sacrificial spacer; selectively etching the dummy polysilicon gate relative to the first ILD layer and the sacrificial spacer; depositing a replacement metal gate (RMG); etching a portion of the RMG to create a recess surrounded by the sacrificial spacer; and depositing a gate capping layer in the recess. The gate capping layer is at least partially surrounded by the sacrificial spacer and is made of silicon oxycarbide (SiOC).