The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 06, 2016
Filed:
Apr. 10, 2015
Applicant:
Globalfoundries Singapore Pte. Ltd., Singapore, SG;
Inventors:
Pengfei Guo, Singapore, SG;
Shyue Seng Tan, Singapore, SG;
Guowei Zhang, Singapore, SG;
Francis Poh, Singapore, SG;
Danny Pak-Chum Shum, Poughkeepsie, NY (US);
Assignee:
GLOBALFOUNDRIES SINGAPORE PTE. LTD., Singapore, SG;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/788 (2006.01); H01L 27/115 (2006.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
H01L 29/42328 (2013.01); G11C 16/0433 (2013.01); H01L 27/11558 (2013.01); H01L 29/42324 (2013.01); H01L 29/66575 (2013.01); H01L 29/66825 (2013.01); H01L 29/7835 (2013.01); H01L 29/7881 (2013.01); H01L 29/7883 (2013.01); H01L 29/7885 (2013.01);
Abstract
Embodiments of a simple and cost-free multi-time programmable (MTP) structure for non-volatile memory cells are presented. The memory cell includes a substrate. A floating gate is disposed over a transistor well. A control gate disposed over a control well is coupled to the floating gate. The control gate includes a control capacitor. A non-self-aligned source/drain (S/D) region is disposed within the transistor well and serves as an erase terminal.