The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 06, 2016
Filed:
Oct. 14, 2014
Denso Corporation, Kariya, Aichi-pref., JP;
Hirotaka Saikaku, Kariya, JP;
Tsuyoshi Yamamoto, Kariya, JP;
Shoji Mizuno, Okazaki, JP;
Masakiyo Sumitomo, Okazaki, JP;
Tetsuo Fujii, Toyohashi, JP;
Jun Sakakibara, Nagoya, JP;
Hitoshi Yamaguchi, Nisshin, JP;
Yoshiyuki Hattori, Aichi-gun, JP;
Rie Taguchi, Toyota, JP;
Makoto Kuwahara, Nagoya, JP;
DENSO CORPORATION, Kariya, JP;
Abstract
A semiconductor device includes a switching element having: a drift layer; a base region; an element-side first impurity region in the base region; an element-side gate electrode sandwiched between the first impurity region and the drift layer; a second impurity region contacting the drift layer; an element-side first electrode coupled with the element-side first impurity region and the base region; and an element-side second electrode coupled with the second impurity region, and a FWD having: a first conductive layer; a second conductive layer; a diode-side first electrode coupled to the second conductive layer; a diode-side second electrode coupled to the first conductive layer; a diode-side first impurity region in the second conductive layer; and a diode-side gate electrode in the second conductive layer sandwiched between first impurity region and the first conductive layer and having a first gate electrode as an excess carrier injection suppression gate.