The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 06, 2016
Filed:
Apr. 26, 2013
California Institute of Technology, Pasadena, CA (US);
Cecile Jung-Kubiak, Pasadena, CA (US);
Theodore Reck, Pasadena, CA (US);
Bertrand Thomas, Bonn, DE;
Robert H. Lin, Chino, CA (US);
Alejandro Peralta, Huntington Beach, CA (US);
John J. Gill, La Crescenta, CA (US);
Choonsup Lee, La Palma, CA (US);
Jose V. Siles, Pasadena, CA (US);
Risaku Toda, Glendale, CA (US);
Goutam Chattopadhyay, Pasadena, CA (US);
Ken B. Cooper, Glendale, CA (US);
Imran Mehdi, South Pasadena, CA (US);
CALIFORNIA INSTITUTE OF TECHNOLOGY, Pasadena, CA (US);
Abstract
A silicon alignment pin is used to align successive layers of components made in semiconductor chips and/or metallic components to make easier the assembly of devices having a layered structure. The pin is made as a compressible structure which can be squeezed to reduce its outer diameter, have one end fit into a corresponding alignment pocket or cavity defined in a layer of material to be assembled into a layered structure, and then allowed to expand to produce an interference fit with the cavity. The other end can then be inserted into a corresponding cavity defined in a surface of a second layer of material that mates with the first layer. The two layers are in registry when the pin is mated to both. Multiple layers can be assembled to create a multilayer structure. Examples of such devices are presented.