The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 29, 2016
Filed:
Sep. 29, 2011
Applicants:
Vinu K. Elias, Austin, TX (US);
Chih-liang Leon Huang, Austin, TX (US);
Inventors:
Vinu K. Elias, Austin, TX (US);
Chih-Liang Leon Huang, Austin, TX (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 3/00 (2006.01); H03K 5/00 (2006.01); H03K 19/0185 (2006.01); H03K 19/0948 (2006.01);
U.S. Cl.
CPC ...
H03K 5/00 (2013.01); H03K 19/018578 (2013.01); H03K 19/09482 (2013.01);
Abstract
Described herein are apparatus, system, and method for reducing electrical over-stress of transistors and for generating an output with deterministic duty cycle for load independent buffers. The apparatus comprises a feedback capacitor electrically coupled between an input terminal and an output terminal of a buffer; and a switch, electrically parallel to the feedback capacitor and operable to electrically short the feedback capacitor in response to a control signal, wherein the switch causes a deterministic voltage level on the input terminal.