The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 29, 2016

Filed:

Jan. 07, 2016
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Bharath Upputuri, Santa Clara, CA (US);

Shreekanth Sampigethaya, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F 1/30 (2006.01); G11C 7/06 (2006.01); G11C 29/02 (2006.01); G01R 27/02 (2006.01); G11C 29/12 (2006.01); H03F 3/45 (2006.01);
U.S. Cl.
CPC ...
H03F 1/301 (2013.01); G01R 27/02 (2013.01); G11C 7/06 (2013.01); G11C 7/065 (2013.01); G11C 29/02 (2013.01); G11C 29/026 (2013.01); G11C 29/028 (2013.01); G11C 29/12 (2013.01); H03F 3/45179 (2013.01); H03F 2200/471 (2013.01); H03F 2203/45588 (2013.01);
Abstract

A sense amplifier includes a first transistor having a first gate, a second transistor having a second gate in series with the first transistor, a third transistor having a third gate, and a fourth transistor having a fourth gate in series with the third transistor. A first input node is coupled to the third gate and the fourth gate, a second input node is coupled to the first gate and the second gate, and a first compensation transistor is in series with the first and second transistors or the third and fourth transistors, the first compensation transistor having a first compensation bulk. The first compensation bulk receives a first compensation voltage to modify the first compensation threshold, the first compensation voltage having a value calculated to compensate for an offset associated with the first and second input nodes.


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