The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 29, 2016

Filed:

Jan. 15, 2013
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Wen-Chung Chang, Hsinchu, TW;

Shen-De Wang, Hsinchu County, TW;

Ya-Huei Huang, Tainan, TW;

Feng-Ji Tsai, Hsinchu, TW;

Chien-Hung Chen, Hsin-Chu, TW;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/115 (2006.01); H01L 29/66 (2006.01); H01L 29/792 (2006.01); H01L 29/423 (2006.01); H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66833 (2013.01); H01L 21/28282 (2013.01); H01L 27/11573 (2013.01); H01L 27/11575 (2013.01); H01L 29/4234 (2013.01); H01L 29/792 (2013.01);
Abstract

A method for manufacturing a non-volatile memory structure includes providing a substrate having a memory region and a logic region defined thereon, masking the logic region while forming at least a first gate in the memory region, forming an oxide-nitride-oxide (ONO) structure under the first gate, forming an oxide structure covering the ONO structure on the substrate, masking the memory region while forming a second gate in the logic region, and forming a first spacer on sidewalls of the first gate and a second spacer on sidewalls of the second gate simultaneously.


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