The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 29, 2016
Filed:
May. 01, 2013
Mitsubishi Electric Corporation, Chiyoda-ku, Tokyo, JP;
Tsuyoshi Kawakami, Tokyo, JP;
Ze Chen, Tokyo, JP;
Akito Nishii, Tokyo, JP;
Fumihito Masuoka, Tokyo, JP;
Katsumi Nakamura, Tokyo, JP;
Akihiko Furukawa, Tokyo, JP;
Yuji Murakami, Tokyo, JP;
Mitsubishi Electric Corporation, Chiyoda-ku, JP;
Abstract
An electric field buffer layer is formed so as to surround an active region. The electric field buffer layer includes a plurality of P-type impurity layers. Each of the P-type impurity layers includes P-type implantation layers and P-type diffusion layers that are formed so as to respectively surround the P-type implantation layers and contain P-type impurities at a concentration lower than that of the P-type implantation layers. A first P-type implantation layer is formed to be in contact with or to partially overlap the active region. Each of the P-type diffusion layers is formed to have an expansion to a degree to which the first P-type diffusion layer is in contact with or overlaps a second P-type diffusion layer. Intervals between the P-type implantation layers increase from the active region toward the outer peripheral portion of the semiconductor substrate.