The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 29, 2016

Filed:

Oct. 17, 2013
Applicant:

Cypress Semiconductor Corporation, San Jose, CA (US);

Inventors:

Chun Chen, San Jose, CA (US);

Kuo-Tung Chang, Saratoga, CA (US);

Shenqing Fang, Sunnyvale, CA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/792 (2006.01); H01L 27/115 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 27/1157 (2013.01); H01L 29/66833 (2013.01); H01L 29/7926 (2013.01); H01L 27/11556 (2013.01);
Abstract

A three-dimensional charge trap semiconductor device is constructed with alternating insulating and gate layers stacked over a substrate. During the manufacturing process, a channel hole is formed in the stack and the gate layers are recessed from the channel hole. Using the recessed topography of the gate layers, a charge trap layer can be deposited on the sidewalls of the channel hole and etched, leaving individual discrete charge trap layer sections in each recess. Filling the channel hole with channel material effectively provides a three-dimensional semiconductor device having individual charge trap layer sections for each memory cell.


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