The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 22, 2016
Filed:
Jan. 13, 2016
Applicant:
Xinnova Technology Limited, Beijing, CN;
Inventors:
Assignee:
XINNOVA TECHNOLOGY LIMITED, Beijing, CN;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 27/115 (2006.01); H01L 21/28 (2006.01); H01L 29/76 (2006.01); H01L 29/788 (2006.01); H01L 29/40 (2006.01); H01L 29/66 (2006.01); H01L 29/423 (2006.01); H01L 21/265 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7883 (2013.01); H01L 21/26513 (2013.01); H01L 21/28273 (2013.01); H01L 27/11521 (2013.01); H01L 29/401 (2013.01); H01L 29/42328 (2013.01); H01L 29/66825 (2013.01); H01L 21/02238 (2013.01); H01L 27/11524 (2013.01);
Abstract
A non-volatile memory unit includes a substrate, a first dielectric layer, an erase gate, a floating gate, a second dielectric layer, a coupled dielectric layer and a couple control gate. The substrate has a source region and a drain region, and the first dielectric layer is formed on the substrate. The erase gate, the floating gate, the second dielectric layer and the selective gate are formed on the first dielectric layer. The second dielectric layer and coupled dielectric layer are formed among and above the erase gate, the floating gate and the selective gate, and the couple control gate is formed on the coupled dielectric layer.