The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 22, 2016

Filed:

May. 25, 2016
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Hans-Peter Moll, Dresden, DE;

Peter Baars, Dresden, DE;

Jan Hoentschel, Dresden, DE;

Assignee:

GLOBALFOUNDRIES Inc., Grand Cayman, KY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/10 (2006.01); H01L 29/76 (2006.01); H01L 31/036 (2006.01); H01L 31/112 (2006.01); H01L 29/78 (2006.01); H01L 29/08 (2006.01); H01L 29/161 (2006.01); H01L 29/165 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7848 (2013.01); H01L 29/0649 (2013.01); H01L 29/0847 (2013.01); H01L 29/161 (2013.01); H01L 29/165 (2013.01); H01L 29/7838 (2013.01);
Abstract

A semiconductor device includes an active region formed in a semiconductor substrate, a gate structure disposed over the active region, source/drain regions formed in the active region in alignment with the gate structure, and a buried insulating material region disposed in the active region under the gate structure. The buried insulating material region is surrounded by the active region and borders a channel region in the active region below the gate structure along a depth of the active region. The source/drain regions have a depth greater than a top surface of the buried insulating material region.


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