The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 22, 2016

Filed:

Aug. 26, 2014
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Guillaume Bouche, Albany, NY (US);

Jason E. Stephens, Albany, NY (US);

Tuhin Guha Neogi, Clifton Park, NY (US);

Mark A. Zaleski, Galway, NY (US);

Andy Chih-Hung Wei, Queensbury, NY (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/417 (2006.01); H01L 29/165 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66545 (2013.01); H01L 29/41783 (2013.01); H01L 29/6653 (2013.01); H01L 21/823871 (2013.01); H01L 27/092 (2013.01); H01L 29/165 (2013.01);
Abstract

An improved semiconductor structure and methods of fabrication that provide improved transistor contacts in a semiconductor structure are provided. A first block mask is formed over a portion of the semiconductor structure. This first block mask covers at least a portion of at least one source/drain (s/d) contact location. An s/d capping layer is formed over the s/d contact locations that are not covered by the first block mask. This s/d capping layer is comprised of a first capping substance. Then, a second block mask is formed over the semiconductor structure. This second block mask exposes at least one gate location. A gate capping layer, which comprises a second capping substance, is removed from the exposed gate location(s). Then a metal contact layer is deposited, which forms a contact to both the s/d contact location(s) and the gate contact location(s).


Find Patent Forward Citations

Loading…