The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9502513 B1

PDF
Full Text
Expired
Date of Patent:
Nov. 22, 2016

Filed:

Jan. 30, 2016
Applicant:

Xinnova Technology Limited, Beijing, CN;

Inventors:

Der-Tsyr Fan, Taoyuan County, TW;

Chih-Ming Chen, Hsin-chu County, TW;

Jung-Chang Lu, Hsin-chu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 29/423 (2006.01); H01L 29/788 (2006.01); H01L 21/28 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/42328 (2013.01); H01L 21/28273 (2013.01); H01L 29/66825 (2013.01); H01L 29/7883 (2013.01);
Abstract

This disclosure discloses a non-volatile memory component and a manufacture method of the same. The non-volatile memory component includes a substrate, a first dielectric layer on the substrate, an erase gate (EG), a floating gate (FG) and a select gate (EG). The substrate includes a source region and a drain region. The erase gate (EG), the floating gate (FG) and the select gate (EG) are formed on the first dielectric layer. Additionally, non-volatile memory component includes a coupling dielectric layer formed in the intervals and the upper region of the erase gate (EG), the floating gate (FG) and the select gate (SG), and a coupling gate (CG) formed on the coupling dielectric layer.


Find Patent Forward Citations

Loading…