The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 22, 2016

Filed:

Nov. 04, 2014
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Hyun-Min Choi, Uiwang-si, KR;

Shigenobu Maeda, Seongnam-si, KR;

Jihoon Yoon, Seoul, KR;

Sungman Lim, Seoul, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/112 (2006.01); H01L 29/06 (2006.01); H01L 29/78 (2006.01); H01L 29/423 (2006.01); H01L 27/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11206 (2013.01); H01L 29/0649 (2013.01); H01L 29/42372 (2013.01); H01L 29/7851 (2013.01); H01L 27/0207 (2013.01);
Abstract

The inventive concepts provide semiconductor devices and methods of manufacturing the same. One semiconductor device includes a substrate, a device isolation layer disposed on the substrate, a fin-type active pattern defined by the device isolation layer and having a top surface higher than a top surface of the device isolation layer, a first conductive line disposed on an edge portion of the fin-type active pattern and on the device isolation layer adjacent to the edge portion of the fin-type active pattern, and an insulating thin layer disposed between the fin-type active pattern and the first conductive line. The first conductive line forms a gate electrode of an anti-fuse that may be applied with a write voltage.


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