The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 22, 2016

Filed:

Nov. 11, 2015
Applicant:

SK Hynix Inc., Icheon-si Gyeonggi-do, KR;

Inventors:

Ki Yong Lee, Seoul, KR;

Jong Hyun Kim, Seoul, KR;

Hyung Ju Choi, Seoul, KR;

Assignee:

SK HYNIX IONC., Icheon-Si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/26 (2014.01); H01L 21/66 (2006.01); H01L 23/00 (2006.01); H05K 1/11 (2006.01); H05K 1/02 (2006.01); G01R 31/28 (2006.01);
U.S. Cl.
CPC ...
H01L 24/85 (2013.01); G01R 31/2806 (2013.01); H01L 22/14 (2013.01); H01L 22/32 (2013.01); H01L 24/05 (2013.01); H01L 24/48 (2013.01); H05K 1/0298 (2013.01); H05K 1/115 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/05025 (2013.01); H01L 2224/48227 (2013.01); H05K 2201/09545 (2013.01);
Abstract

A method of manufacturing a semiconductor package is provided. The method includes providing a strip substrate having a plurality of unit substrate regions that are spaced apart from each other by a periphery region and have blind vias, a peripheral conductive pattern layer disposed in the periphery region, and a connection pattern layer electrically connecting the blind vias to the peripheral conductive pattern layer. Semiconductor chips are disposed on the plurality of unit substrate regions, respectively. Conductive wires are formed to electrically connect connection pads disposed on the plurality of unit substrate regions to bonding pads disposed on the semiconductor chips. The connection pads are electrically connected to the blind vias, and forming the conductive wires includes performing a test for confirming a current that flows between each conductive wire and the peripheral conductive pattern layer through the unit substrate region.


Find Patent Forward Citations

Lee, Ki. (2016). Printed circuit boards having blind vias, method of testing electric current flowing through blind via thereof and method of manufacturing semiconductor packages including the same (U.S. Patent No. 9502378). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9502378

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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