The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 22, 2016
Filed:
Feb. 26, 2014
Applicant:
Nvidia Corporation, Santa Clara, CA (US);
Inventor:
Leilei Zhang, Sunnyvale, CA (US);
Assignee:
NVIDIA Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 21/56 (2006.01); H01L 21/50 (2006.01); H01L 25/065 (2006.01); H01L 25/10 (2006.01); H01L 25/00 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5389 (2013.01); H01L 21/50 (2013.01); H01L 21/56 (2013.01); H01L 23/49811 (2013.01); H01L 25/0652 (2013.01); H01L 25/0655 (2013.01); H01L 25/105 (2013.01); H01L 25/50 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 24/81 (2013.01); H01L 24/83 (2013.01); H01L 2224/131 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16235 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/81903 (2013.01); H01L 2224/83101 (2013.01); H01L 2224/83851 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/1023 (2013.01); H01L 2225/1041 (2013.01); H01L 2225/1058 (2013.01); H01L 2924/12041 (2013.01); H01L 2924/12042 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/15331 (2013.01);
Abstract
A system, method, and computer program product are provided for producing a high bandwidth bottom package of a die-on-package structure. The method includes the steps of receiving a bottom package comprising a substrate material having a top layer and an integrated circuit die that is coupled to the top layer of the substrate material. A first set of pads is formed on the top layer of the substrate material and a layer of dielectric material is applied on a top surface of the bottom package to cover the integrated circuit die and the first set of pads.