The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 22, 2016

Filed:

Nov. 16, 2015
Applicant:

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Inventors:

Xiaoyan Bao, Shanghai, CN;

Hongtao Ge, Shanghai, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 23/31 (2006.01); H01L 27/06 (2006.01); H01L 21/033 (2006.01); H01L 21/768 (2006.01); H01L 21/311 (2006.01); H01L 49/02 (2006.01); H01L 21/288 (2006.01); H01L 21/321 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5227 (2013.01); H01L 21/0332 (2013.01); H01L 21/2885 (2013.01); H01L 21/31144 (2013.01); H01L 21/3212 (2013.01); H01L 21/7684 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 23/3171 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 23/53228 (2013.01); H01L 27/0617 (2013.01); H01L 27/0641 (2013.01); H01L 27/0676 (2013.01); H01L 28/10 (2013.01);
Abstract

A method for forming a semiconductor device includes, sequentially, providing a substrate having a first region and a second region; forming a first dielectric layer on the substrate; forming a second dielectric layer having a plurality of first openings exposing portions of a top surface of the first dielectric layer; forming a first conductive layer in the first openings; etching the second dielectric layer and the first dielectric layer in the second region until the substrate is exposed to form a plurality of second openings; forming passivation regions in portions of the substrate exposed by the second openings; exposing the surface of the first dielectric layer in the second region; forming a third dielectric layer on the surface of the first dielectric layer and in the second openings; and forming a second conductive layer, a portion of which is configured as an inductor, over the third dielectric layer.


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