The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9502337 B1

Date of Patent:

Nov. 22, 2016

Filed:

Oct. 29, 2015

Flip-chip on leadframe semiconductor packaging structure and fabrication method thereof

Applicant:

Nantong Fujitsu Microelectronics Co., Ltd., Nantong, CN;

Inventor:

Lei Shi, Nantong, CN;

Assignee:

NANTONG FUJITSU MICROELECTRONICS CO., LTD., Nantong, CN;

Attorney:

Anova Law Group, PLLC

Primary Examiner:

Alonzo Chambliss

Int. Cl.

CPC ...

H01L 23/495 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 21/78 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01); H01L 21/60 (2006.01);

U.S. Cl.

CPC ...

H01L 23/49558 (2013.01); H01L 21/4825 (2013.01); H01L 21/4835 (2013.01); H01L 21/561 (2013.01); H01L 21/565 (2013.01); H01L 21/78 (2013.01); H01L 23/3114 (2013.01); H01L 23/49575 (2013.01); H01L 24/14 (2013.01); H01L 24/17 (2013.01); H01L 24/81 (2013.01); H01L 23/49582 (2013.01); H01L 2021/60022 (2013.01); H01L 2924/18161 (2013.01);

Abstract

Flip-chip on leadframe (FCOL) semiconductor packaging structure and fabrication method thereof are provided. A semiconductor chip with copper pillars formed there-over is provided. A barrier layer is formed on the copper pillars. A solder material is coated on the barrier layer. A layer of soldering flux is coated on the solder material. A leadframe with electric leads formed thereon is provided. An insulating layer is formed an the leadframe and having a plurality of openings to expose portion of the electric leads. The semiconductor chip is placed upside down onto the leadframe to have the soldering flux in contact with the portion of the electric leads exposed in the openings. The solder material flows back to form conductive interconnections between the copper pillars and the portion of the electric leads exposed in the openings. The semiconductor chip is packaged with the leadframe using a mold compound.

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Shi, Lei. (2016). Flip-chip on leadframe semiconductor packaging structure and fabrication method thereof (U.S. Patent No. 9502337). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9502337

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